The Impact of the Changing Semiconductor Landscape on Third-Party IP Suppliers

By Walter Ng
Vice President, Design Enablement Alliances
Chartered Semiconductor Manufacturing

Technology marches on

There is no question that 32 nanometer is fast becoming a reality, and it is no longer a distant point on a technology roadmap. We're past the discussions and debate on how the industry will technically reach that next node (we are splitting atoms after all). Through innovation, invention in materials science and equipment, collaboration, and enablement - the industry will make the next node work once again.

As we move down the technology curve, the industry has managed to even accelerate the time between nodes. But what are the business repercussions of this accelerated march, especially in the context of dramatic increases in cost and complexity associated with the move to 32nm? Undeniably, the business landscape is being altered, forcing companies to re-examine strategies and priorities, most notably foundries and third-party IP suppliers. Some will prosper, some will fall by the wayside and many will emerge with vastly different survival strategies.

For third-party IP suppliers, the decision comes down to weighing the risks and opportunities available in the new industry landscape that 32nm technology presents. There will be fewer players for sure, but the opportunities may be larger than ever for the right set of suppliers.

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The Push to 32nm

Demand for increased functionality and performance enhancements means that the semiconductor companies supplying new and improved games, graphics, mobile internet devices, smart phones and digital home products are continually pushing foundries for the next-generation process technology. The old adage of "smaller-faster-cheaper" still holds true; the only caveat is that it now includes "more features" and an increased emphasis on "cheaper." Customers want to enable higher levels of integration in support of more and more product capabilities. The big companies want to keep ahead of the competition - driving smaller companies that are not able to integrate as well further behind or into more niche markets. Moving to 32nm provides a performance boost, and it will also lower the cost per die. So the lead pack forges ahead, creating a high-stakes game of "chicken" - if you can't compete, get out of the way.

While process technology development is being pushed hard by the industry leaders, the gap is widening between the second wave of technology adopters as fewer and fewer companies have the resources to keep pushing development at breakneck pace. They can't - or won't - keep up with the pace of the lead pack, and this is significantly altering the industry landscape, creating real quandaries for foundries and third-party IP companies.

What This Means for Foundries

The temptation for everyone in the industry is to blindly move to the next technology node because that is what we have always done. But for foundries, the push to the next node requires serious scrutiny. In the past, the foundry industry has been fortunate in having been able to ride the relatively straightforward path of scaling to each new node. But we all know that at 32nm and beyond, "scaling is dead." To continue to be able to deliver process technologies at 32nm and beyond requires unprecedented technology innovation. Fueling technology innovation requires a serious deep semiconductor research capability, based on proven talent and new level of focus on materials science. That type of commitment requires the patience and depth of very long-term investment, the scale of which only a few prominent companies can handle.

It is safe to say that short list does not include a foundry on its own. As a result, collaborations and other relationships, which give foundries access to such capabilities and knowledge, will be critical. Even if a foundry is able to access technology innovation, it continues to be a significant investment on three fronts.

Let's start with process development. The investment in process development for leading-edge technologies has never been greater. Process R&D costs for the 32nm node are estimated to be about $3 billion. With process R&D costs skyrocketing, many traditional semiconductor players simply cannot justify the cost and are moving out of process development.

Some companies, like Chartered Semiconductor Manufacturing, are addressing this technology and economic challenge through collaboration. Since the 90nm process technology node, Chartered has been working with IBM in a joint development alliance (JDA) on process technology. In this model, we share costs and resources, while leveraging each company's expertise in key areas, like materials science, manufacturing, and consumer requirements. The JDA through 65nm and 45nm development has flourished by growing in breadth - now including design enablement and DFM (design for manufacturing) - and in depth with the number of alliance partners going from two at 90nm to seven at 32nm. At 32nm, Chartered is working with IBM, Samsung, Infineon, Freescale, ST Microelectronics and Toshiba. The collaboration allows the continued melting pot of expertise of seven of the premier semiconductor companies in the world, working together on the world's leading process technology, but also in the best economical model in the semiconductor industry today. This shared cost model leverages technology flowing from IBM's premier research facilities including the T.J.Watson Labs being shaped through the Albany Nanotechnology center, then implemented in IBM's 300mm fab in Fishkill, N.Y., headquarters for the JDA.

R&D costs are just part of the equation and strategic investment decision. Another major consideration is the cost of fabs. With fab costs projected to top $5 billion for 32nm, few companies can afford the investment in their own fabs, as more companies continue to go fab-lite or fabless. IC Insights (Scottsdale, AZ) estimates for a company manufacturing its own products at 32nm to achieve an acceptable ROI, it must generate more than $16 billion in annual revenue. There are very few companies in the world that generate that kind of revenue.

Finally there is the investment required to put in place design enablement to enable customers to more easily design on a given process. This includes libraries, IP and design flow / EDA support. As design at the leading edge continues to grow in complexity, the costs of putting this design infrastructure in place is also a significant investment in both dollars and resources. Each new technology node requires significant improvements in modeling and support in EDA tools and design flows. In recent history, many industry observers generalized such effects under the DFM label and as we have seen, tighter levels of collaboration in such areas are required as we move forward to 32nm.

Third-Party IP Suppliers Weigh High-Risk Tradeoffs

Semiconductor companies and foundries aren't the only ones making business-altering decisions, as they consider moving to 32nm and beyond. Third-party IP suppliers appear to also be taking a harder look at when - or if - it makes sense to move to the next technology node.

While there may be fewer companies adopting cutting-edge technology early on, as we move forward to 32nm, the ones pushing on technology are large, significant industry leaders not easily ignored. Often, these technology drivers are accustomed to relying on their own IP, because as they move to a new technology node, little if any third-party IP is commercially available. While it may initially seem that the leading edge is offering fewer opportunities for third-party IP suppliers, there is in fact a large potential market for those IP suppliers who can satisfy the early adopters' specific needs for outsourced IP. Most of the lead drivers are under time-to-market as well as cost and resource pressures. Internal resources are valuable and targeted toward the high value differentiated IP development.

For many, development of non-differentiated foundation or standard interface IP is a necessary evil. If that class of IP existed prior to their own investment in the development, it would be a simple make-versus-buy decision, and probably favor the 'buy' option. IP providers must weigh the risks against the benefits at the leading edge: less competition, higher prices, and ultimately, higher margins. The stakes may have significant implications to success or failure of a third-party IP supplier. Those who decide to forge ahead and develop for the leading-edge processes early enough to engage business from the large leaders will benefit from the technical and business relationships which develop as part of the requirement of a close development engagement. Other benefits include valuable early design/process experience and early access to process deliverables so that IP designs would be proven and stable for other potential customers to follow. The risk for those who do so and are unsuccessful in winning business with the lead pack of customers is that they would likely have to wait until the next wave, which may be two years behind, before their investment may be recouped.

Deciding not to move to the next node early also has its own set of business-altering potentials. Focusing on the IP business solely at the mainstream process nodes means focusing on where there may be more opportunities, but also much more competition for those spots. It also inevitably means selling/licensing IP at lower prices and thus lower margins. For less established IP suppliers, this may be a difficult arena to compete, without deep customer relationships. The other drawback in purely focusing on the mainstream nodes is that it will always be a follower strategy with challenges in developing differentiation from an offering and a pricing standpoint.

Our industry is remarkably consistent in its ability to maintain the pace of progression when it comes to process technology. 32nm process technology is real and will be available to the masses very soon. Technology innovation has led to the development of high-k metal gate (HKMG) which an essential ingredient in meeting customers/designers expectations in the areas of power and performance at the 32nm process technology node. Foundries and certain manufacturers have invested many years ahead to enable the process and manufacturing for 32nm. EDA has been partnering over the past year with manufacturers on ensuring their tools are able to support design at 32nm. The lead customers are engaged and already beginning with the business of design.

The question to the third-party IP industry is whether there are enough leaders to forge ahead and ensure third-party IP availability as the customers need, or will this problem need to be resolved in other ways?

The stakes have never been higher.

Explore IP from the Common Platform

Chartered, along with its Common Platform partners, IBM and Samsung, will be presenting more information on 32nm and high-k metal gate at the Common Platform Tech Forum on Tuesday, September 30 at the Santa Clara Convention Center, Santa Clara, Calif. For more information, visit www.commonplatform.com.

About the Author

Walter Ng reports to the Senior Vice President of Technology Development and is responsible for identifying, developing and executing customer and partner alliances that advance the adoption of Chartered's solutions for the leading-edge and mainstream technology nodes. Walter has led the company's collaboration with IBM to define the strategy and implementation of the solutions and third-party network for the industry's first common design enablement platform at 90 nanometer (nm) and 65nm while currently driving 45nm and setting strategy for 32nm. Previously, Walter served as senior director of design solutions and was responsible for driving and managing Chartered's relationships with third-party EDA and IP partners. Walter has been in the electronic design and EDA industry for nearly 20 years. Prior to joining Chartered, Walter was Director of Business Development and Asia Pacific Operations with Sequence Design. In this position, he was responsible for establishing, managing and growing Sequence Design's Asia Pacific sales channel and marketing activities in addition to managing the strategic relations program for foundries, EDA and IP partners. From 1994 to 1999, Walter worked with Cadence Design Systems, where he held positions in strategic marketing and numerous roles in applications engineering, consulting services, sales support and marketing. Previously, he has held various senior design and test engineering positions in Raytheon's Equipment Development Labs. Walter holds a B.S. in Electrical Engineering from the University of Massachusetts, Amherst, and an M.B.A from the University of Massachusetts, Boston.